wiki:Hardware/sdr/usrp2974

Site Navigation

  1. COSMOS Testbed Overview
    1. Concepts
    1. Testbed Workflow
    1. Availability and Resource Status
    1. Events and Conferences
  6. Getting Started
    1. Make an Account
    2. Create and Configure SSH Keys
    3. Make a Reservation
    4. Log in to your Reservation
    5. Control Resources with OMF
    6. Run a Hello World Experiment
    7. Get Help and Support
  7. User Guide
    1. Policies
    1. Account Creation
    1. Scheduling and Reservations
    1. Disk Images
    1. Frequently Asked Questions
    1. Resource Control with OMF
    1. Remote Access
    1. Chrome Remote Desktop Setup Page
    1. Measurement & Result Collection
    1. Storage
    1. Support
    1. Contributing to the Wiki
  20. Tutorials
    1. SDR and Wireless
    2. Optical Networking
    3. Wired Networking
    4. Edge Computing
    5. 4G/5G Systems
    6. Orchestration Platforms
  21. Architecture
    1. Data Flow
    1. Deployment Map
    1. Domains
    1. Naming Convention
    1. Networks
    1. Optical
  28. Resources, Services and APIs
    1. RF Control
    2. SDR Control
    3. Compute Control
    4. Network Control
    5. Optical Control
  29. Datasets
  30. Hardware Info
    1. Cameras
    1. Compute
    1. Network
    1. Nodes
    1. Optical
    1. RF Subsystems
    1. Antennas
    1. Full-Duplex Radio
    1. RF Front End
    1. Software Defined Radios (SDR)
  41. RF Policies & Compliance
    1. Outdoor Radio Frequency Allocation
    2. Program Experiment License
    3. Spectrum Monitoring
    4. Emergency Stop Procedures
    5. Network and Platform Security

USRP 2974

The USRP 2974 combines a high performance Intel based embedded mini-pc with a USRP X310, with integrated daughterboards.

Due to this combination, it is both a Compute Resource, as well as an SDR Resource.

Further Information can be found at ​Ettus Research

Block Diagram

The connection between the embedded PC and the FPGA can be done either over internal PCIe3.0 x4, or over internal 10G ethernet.

External data connections max out at 10 gigabits per second each, to the embedded PC and to the FPGA.

It is possible to bridge and forward the traffic from the internal 10g connection over SFP0, but this is untested and unsupported.

Last modified 5 years ago Last modified on May 11, 2020, 3:32:26 AM

Attachments (1)

Download all attachments as: .zip

Note: See TracWiki for help on using the wiki.